1. Field of the Invention
The present invention relates generally to parallel operation processing devices, and more specifically, to an instruction fetching method in a superscalar type processor (hereinafter simply referred to as a superscalar).
2. Description of the Background Art
The superscalar is a processor including the following features:
(1) fetching of a plurality of instructions at a time,
(2) provision of a plurality of function units, and execution of a plurality of instructions at a time using these units, and
(3) finding of instructions which can be executed at a time among the plurality of instructions fetched at a time, and dispatching of these simultaneously executable instructions to corresponding function units.
FIG. 1 is a diagram showing a general structure of a superscalar. In FIG. 1, the superscalar includes an instruction cache (instruction memory) 1 for storing instructions, an instruction fetch stage (IF) 2 for transmitting the addresses of instructions to be fetched to instruction memory 1, and an instruction decode stage (ID) 3 for executing operations such as decoding of the plurality of instructions fetched from instruction memory 1, reading of an instruction of a register file, and executing of a branch instruction. Instruction decode stage (ID) 3 also has a function of finding simultaneously executable instructions from the decoded plurality of instructions and dispatching (issuing) these simultaneously executable instructions to corresponding ones among function units 4a, 4b, 5 and 6. Function units 4a, 4b, 5 and 6 can execute instructions in parallel with each other. Provided in the structure shown in FIG. 1 are integer calculation units 4a and 4b for executing integer addition, etc., a unit 5 for executing storing of data to a data cache (data memory) 7 or loading of the data therefrom, and a unit 6 for executing a floating point operation.
In the superscalar, instruction fetch stage (IF stage) 2, instruction decode stage (ID stage) 3 and functional units 4a, 4b, 5 and 6 are pipelined. Function units 4a and 4b include an execution stage EXC for executing an instruction given from decode stage 3, and a write back stage (WB stage) for writing the result of the execution to a register file (not shown).
A memory access unit 5 includes an address calculation stage (ADR stage) for calculating the address of data cache 7 in accordance with an instruction from instruction decode stage 3, a memory access stage (MEM stage) for making an access to data cache 7 in accordance with the calculated address, and a write back stage (WB stage) for writing the loaded data from data cache 7 to the register file.
Floating point operation unit 6 includes three instruction stages, EXC1, EXC2, and EXC3 for executing an instruction from instruction decode stage 3, and a write back stage WB for writing the result of the execution to the register file.
In the superscalar, as described above, a plurality of instructions from instruction cache 1 are fetched at a time. Among the plurality of instructions simultaneously fetched, instructions which can be executed simultaneously are found in instruction decode stage 3 and the found out instructions are issued to corresponding function units. Function units 4a, 4b, 5 and 6 can execute instructions in parallel with each other. In the superscalar, an improved processing speed can be provided as compared to a usual processor, because a plurality of instructions are executed at a time.
FIG. 2 schematically shows the structure of the essence of an instruction fetch stage (IF) and an instruction decode stage (ID stage) in a conventional superscalar. In the structure of the superscalar shown in FIG. 2, four instructions are simultaneously fetched and decoded.
In FIG. 2, the instruction fetch stage (IF) includes a program counter (PC) for holding the first instruction address of a plurality of instructions to be fetched from instruction cache 1. In the instruction fetch stage (IF), program counter 8 applies a pointer IC.sub.-- addr to instruction cache 1, and reads corresponding instructions (four instructions) simultaneously. The address from program counter 8 is subjected to addition of 16 in an adder 9 (if all the four instructions are issued). The output of adder 9 provides a fetch address in the next cycle. The address from program counter 8 is of 30 bits &lt;31:2&gt;, and the more significant 28 bits &lt;31:4&gt; are applied to instruction cache 1. The term &lt;31:2&gt; indicates that the most significant address bit is A31, and the least significant address bit is A2.
Instruction cache 1 reads the four instructions in accordance with the address &lt;31:4&gt; of the applied 28 bits, asserts a signal IC.sub.-- ready indicating the reading of these instructions, transmits the signal onto a signal line 10, and transmits data IC.sub.-- data onto an instruction bus 11.
A misalignment calculation unit 17 calculates the boundary of words among the four instructions (IR1, IR2, IR3, and IR4) read out from instruction cache 1, or the data IC.sub.-- data, and calculates a signal misalign representing the boundary. The calculation of the boundary of words is executed based on an address &lt;3:2&gt; of the less significant 2 bits from program counter, which will later be described in detail.
Instruction decode stage (ID stage) includes instruction registers 12a, 12b, 12c, and 12d for temporarily latching instructions read out from instruction cache 1, an instruction decoder 13 for decoding the instructions IR1, IR2, IR3, and IR4 stored in instruction registers 12a-12d, and a register 14 for latching the signal IC.sub.-- ready from instruction cache 1.
The instructions IR1, IR2, IR3, and IR4 from instruction cache 1 are unconditionally written in instruction registers 12a-12d. The data IC.sub.-- data from instruction cache 1 includes four parallel instructions IR1, IR2, IR3, and IR4.
Whether or not the instructions written in instruction registers 12a-12d are available is determined based on whether or not the signal IC.sub.-- ready generated from instruction cache 1 is on. Register 14 latches the signal IC.sub.-- ready for indicating whether or not the instructions IR1-IR4 stored in instruction registers 12a-12d are available. The latch signal is herein designated with the prefix "ia".
Instruction decoder 13 produces operation codes, code 1, code 2, code 3, and code 4 for indicating executions in related function units based on instruction codes preprogrammed therein, and transmits the produced codes onto signal lines 15a, 15b, 15c, and 15d, respectively. Instruction decoder 13 also transmits, with respect to instructions which can be issued to the function units, flags ia.sub.-- out 1, ia.sub.-- out 2, ia.sub.-- out 3, and ia.sub.-- out 4 for indicating that these instructions are issuable (available) onto signal lines 16a, 16b, 16c, and 16d.
These operation codes, code 1-code 4 and availability flags ia.sub.-- out 1-ia.sub.-- out 4 are transmitted to the execution stages EXEC1 or ADR of corresponding function units, respectively.
These operation codes, code 1-code 4 are executed in the corresponding function units, respectively. Various methods are embodied or proposed for the manner of the execution. Generally, an operation is executed in a corresponding function unit in accordance with an applied operation code.
Four instructions are simultaneously read out from instruction cache 1. However, as will be described later in detail, it is not possible to read simultaneously from instruction cache 1, four instructions from arbitrary addresses. The addresses at which the four instructions can be read out from instruction cache 1 at a time are provided by the boundary of four words. A description of the reading of these four instructions will be provided with reference to the states shown below in which instructions are stored in instruction cache 1.
______________________________________ Address Instruction ______________________________________ 4n Instruction 0 4n + 4 Instruction 1 4n + 8 Instruction 2 4n + 12 Instruction 3 4 (n + 4) Instruction 4 Boundary of 4 words 4 (n + 4) + 4 Instruction 5 4 (n + 4) + 8 Instruction 6 4 (n + 4) + 12 Instruction 7 ______________________________________
If a fetch address (the output PC of program counter) is 4n, the instruction 0, instruction 1, instruction 2, and instruction 3 can be read out. If the fetch address (pointer PC) is 4n+8, the instructions 2, instructions 3, instruction 4, and instruction 5 can not be read out. Instruction cache 1, in this case, outputs the instruction 0, instruction 1, instruction 2, and instruction 3. When instruction decode stage (ID stage) takes the applied instruction into instruction register 12, instruction registers 12c and 12d take in instructions applied as IR3 and IR4, but instruction registers 12a and 12b do not take in the applied instructions, instruction 0 and instruction 1 as instructions IR1 and IR2. Registers 12a and 12b are reset. More specifically, registers 12a and 12b store an instruction "hop (no operation)".
Information for resetting instruction register 12 is produced by calculating the shift or displacement of the pointer PC generated from program counter (PC) 8 from the boundary of four words, or the amount of misalignment. The calculation of the misalignment amount is executed by misalignment calculation unit 17. Misalignment calculation unit 17 produces information misalign on misalignment from the PC &lt;3:2&gt; of the less significant 2 bits of pointer PC from program counter 8 and transmits the produced information to instruction register 12. The misalignment information misalign has three bits &lt;3:1&gt;, and the bits of the three bit data &lt;3:1&gt; are provided to instruction registers 12a, 12b, and 12c, respectively. Adder 9 adds the value of the number of issued instructions.times.4 to the pointer PC by a signal from a path (not shown) from instruction decoder 13.
FIG. 3A is a representation showing in a table, a logic executed by this misalignment calculation unit 17, and FIG. 3B shows the logical structure of misalignment calculation unit 17. When the pointer PC &lt;3:2&gt; is, for example, "00", it means that instructions from the boundary of words are read out. More specifically, the amount of misalignment in this case is 0. Misalignment information, misalign &lt;3:1&gt;, resets register 12a, registers 12a and 12b, register 12a, and registers 12b and 12c in accordance with the amounts of misalignment 0, 1, 2, and 3, respectively. As shown in FIG. 3C, following four instructions are not fetched until a group of four instructions are all issued. This group of four instructions are repeatedly fetched until all of them are issued.
Four instructions can only be read out simultaneously from the boundary of the four words of instruction cache 1, because cache memory 1 is formed of four memories, and the four memories are accessed by one address IC.sub.-- addr. This structure is shown in FIG. 4.
In FIG. 4, instruction cache 1 includes four memories 19a, 19b, 19c and 19d. Memory 19a stores an instruction of an address 16m (m is an arbitrary integer). Memory 19b stores an instruction of an address 16m+4. Memory 19c stores an instruction of an address 16m+8. Memory 19d stores an instruction of an address 16m+12. One instruction is of 32 bits and stored over four addresses.
The same fetch address IC.sub.-- addr is applied to these four memories 19a-19d. Instructions to be read simultaneously are stored in the same addresses of memories 19a-19d. Therefore, serial four instructions, an instruction 4M, an instruction 4M+1, an instruction 4M+2, and an instruction 4M+3 are read out from cache 1 from the address 16m of the four word boundary. However, four instructions starting at an address which does not lie at the four word boundary, for example, an address of 16m+4, can not be read out simultaneously. In that case, the instructions of addresses 16m, 16m+4, 16m+8, and 16m+12 are again read out. It is to be noted that the fetch address IC.sub.-- addr does not include the less significant 2 bits &lt;3:2&gt; among the pointer PC &lt;31:2&gt; of program counter 8.
Producing two fetch addresses and providing a circuit for shifting an output from instruction cache 1 in accordance with the address values make it possible to read four instructions from an arbitrary address from instruction cache 1. The provision of such a structure however increases the time for accessing instruction cache 1 and impairs the high speed operation of a processor.
The conventional method of fetching an instruction which does not exist at a four word boundary requires a resetting circuit for instruction registers 12a, 12b, and 12c. The number of transistors necessary for instruction register 12 increases as a result, resulting in a disadvantage in terms of power consumption, area occupied by a chip, etc.
FIG. 5 shows the structure of a conventional latch circuit generally for use in a register, and FIG. 6 shows the structure of a latch circuit with a resetting terminal. A signal "clock" shown in FIGS. 5 and 6 is a clock for driving this superscalar, and defines the cycle of pipelining operation.
An inverter circuit requires two transistors at minimum, i.e. complementarily connected a p channel MOS (insulating gate type field effect) transistor and an n channel MOS transistor. In the case of the structure of the latch circuit shown in FIG. 5, ten transistors are necessary accordingly.
The structure of the latch circuit with resetting terminal shown in FIG. 6 requires a two-input NOR circuit for implementing its resetting function. The two-input NOR circuit usually includes two n channel MOS transistors OR-connected for discharging an output portion, and two AND-connected p channel MOS transistor for charging the output portion. That is, NOR circuit NR2 requires four transistors. The latch circuit with resetting terminal shown in FIG. 6 therefore requires 12 transistors all together.
As for instruction register 12 shown in FIG. 2, with the latch circuit with resetting terminal being used for three instruction registers 12a, 12b, and 12c, extra 192 (2.times.32.times.3) transistors will be necessary as compared to a structure using a usual latch circuit (the length of instruction is 32 bits).
In the latch circuit with resetting terminal (see FIG. 6), time delay is greater due to its gate circuit for resetting as compared to the usual latch circuit shown in FIG. 5, which gives rise to extension of the cycle time.